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? semiconductor components industries, llc, 2002 january, 2002 rev. 0 1 publication order number: ncp1200a/d ncp1200a product preview pwm current-mode controller for universal off-line supplies featuring low standby power housed in so8 or dip8 package, the ncp1200a enhances the previous ncp1200 series by offering a reduced optocoupler current together with an increased drive capability. thanks to its novel concept, the circuit allows the implementation of complete offline ac/dc adapters, battery charger or a smps where standby power is a key parameter. with an internal structure operating at a fixed 40 khz, 60 khz or 100 khz, the controller supplies itself from the highvoltage rail, avoiding the need of an auxiliary winding. this feature naturally eases the designer task in battery charger applications. finally, currentmode control provides an excellent audiosusceptibility and inherent pulsebypulse control. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the socalled skip cycle mode and provides excellent efficiency at light loads. because this occurs at a user adjustable low peak current, no acoustic noise takes place. the ncp1200a features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses while the device enters a safe burst mode, trying to restart. once the default has gone, the device autorecovers. features ? no auxiliary winding operation ? autorecovery internal output shortcircuit protection ? extremely low noload standby power ? currentmode control with skipcycle capability ? internal temperature shutdown ? internal leading edge blanking ? 250 ma peak current capability ? internally fixed frequency at 40 khz, 60 khz and 100 khz ? direct optocoupler connection ? spice models available for transient and ac analysis ? pin to pin compatible with ncp1200 typical applications ? ac/dc adapters for portable devices ? offline battery chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. so8 d1, d2 suffix case 751 1 8 device package shipping ordering information tbd tbd marking diagrams pin connections tbd pdip8 n suffix case 626 1 8 http://onsemi.com 1 8 tbd tbd 1 8 xx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 adj 8 hv 2 fb 3 cs 4 gnd 7 nc 6 v cc 5 drv (top view) miniature pwm controller for high power ac/dc wall adapters and offline battery chargers
ncp1200a http://onsemi.com 2 figure 1. typical application example emi filter universal input + + ncp1200a + v out adj fb cs gnd hv v cc drv 1 2 3 4 8 7 6 5 pin function description pin no. pin name function pin description 1 adj adjust the skipping peak current this pin lets you adjust the level at which the cycle skipping process takes place. shorting this pin to ground, permanently disables the skip cycle feature. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 cs current sense input this pin senses the primary current and routes it to the internal comparator via an l.e.b. 4 gnd the ic ground 5 drv driving pulses the driver's output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 10 m f. 7 nc this unconnected pin ensures adequate creepage distance. 8 hv generates the v cc from the line connected to the highvoltage rail, this pin injects a constant current into the v cc bulk capacitor.
ncp1200a http://onsemi.com 3 figure 2. internal circuit architecture overload? uvlo high and low internal regulator 250 ma hv current source internal v cc 8 7 6 5 hv nc v cc drv 1 2 3 4 q flipflop dcmax = 80% q 250 ns l.e.b. 4061100 khz clock - + - + 80 k 20 k 57 k 1 v current sense ground fb adj 24 k 25 k + v ref reset 1.2 v skip cycle comparator set fault duration 5 v maximum ratings rating symbol value unit power supply voltage v cc 16 v thermal resistance junctiontoair, pdip8 version thermal resistance junctiontoair, soic version r q ja r q ja 100 178 c/w c/w maximum junction temperature t j(max) 150 c temperature shutdown 140 c storage temperature range 60 to +150 c esd capability, hbm model (all pins except v cc and hv) 2.0 kv esd capability, machine model 200 v maximum voltage on pin 8 (hv), pin 6 (v cc ) grounded 450 v maximum voltage on pin 8 (hv), pin 6 (v cc ) decoupled to ground with 10 m f 500 v
ncp1200a http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic symbol pin min typ max unit dynamic selfsupply (all frequency versions, otherwise noted) v cc increasing level at which the current source turnsoff v cc(off) 6 11.2 12.1 13.1 v v cc decreasing level at which the current source turnson v cc(on) 6 9.0 10 11 v v cc decreasing level at which the latchoff phase ends v cc(latch) 6 5.4 v internal ic consumption, no output load on pin 6 icc1 6 700 930 (note 1) m a internal ic consumption, 1.0 nf output load on pin 6, f sw = 40 khz icc2 6 1.2 1.4 (note 2) ma internal ic consumption, 1.0 nf output load on pin 6, f sw = 60 khz icc2 6 1.3 1.9 (note 2) ma internal ic consumption, 1.0 nf output load on pin 6, f sw = 100 khz icc2 6 2.2 2.7 (note 2) ma internal ic consumption, latchoff phase icc3 6 340 m a internal startup current source (t j > 0 c) highvoltage current source, v cc = 10 v ic1 8 4.0 7.0 ma highvoltage current source, v cc = 0 ic2 8 13 ma drive output output voltage risetime @ cl = 1.0 nf, 1090% of output signal t r 5 67 ns output voltage falltime @ cl = 1.0 nf, 1090% of output signal t f 5 25 ns source resistance r oh 5 27 41 61 w sink resistance r ol 5 5.0 10 21 w current comparator (pin 5 unloaded) input bias current @ 1.0 v input level on pin 3 i ib 3 0.02 m a maximum internal current setpoint i limit 3 0.8 0.9 1.0 v default internal current setpoint for skip cycle operation i lskip 3 360 mv propagation delay from current detection to gate off state t del 3 90 160 ns leading edge blanking duration t leb 3 230 ns internal oscillator (v cc = 11 v, pin 5 loaded by 1.0 k ) oscillation frequency, 40 khz version f osc 36 42 48 khz builtin frequency jittering, f sw = 40 khz f jitter khz oscillation frequency, 60 khz version f osc 52 61 70 khz builtin frequency jittering, f sw = 60 khz f jitter khz oscillation frequency, 100 khz version f osc 86 103 116 khz builtin frequency jittering, f sw = 100 khz f jitter khz maximum dutycycle dmax 74 80 87 % feedback section (v cc = 11 v, pin 5 loaded by 1.0 k ) internal pullup resistor r up 2 20 k w pin 3 to current setpoint division ratio i ratio 3.3 skip cycle generation default skip mode level v skip 1 0.95 1.1 1.45 v pin 1 internal output impedance z out 1 22 k w 1. max value at t j = 0 c. 2. maximum value @ t j = 25 c, please see characterization curves.
ncp1200a http://onsemi.com 5 application information introduction the ncp1200a implements a standard current mode architecture where the switchoff time is dictated by the peak current setpoint. this component represents the ideal candidate where low partcount is the key parameter, particularly in lowcost ac/dc adapters, auxiliary supplies, etc. thanks to its highperformance highv oltage technology, the ncp1200a incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, lowpass filter and selfsupply. this later point emphasizes the fact that on semiconductor's ncp1200a does not need an auxiliary winding to operate: the product is naturally supplied from the highvoltage rail and delivers a v cc to the ic. this system is called the dynamic selfsupply (dss). dynamic selfsupply the dss principle is based on the char ge/discharge of the v cc bulk capacitor from a low level up to a higher level. we can easily describe the current source operation with a bunch of simple logical equations: poweron: if v cc < vcc h then current source is on, no output pulses if v cc decreasing > vcc l then current source is off, output is pulsing if v cc increasing < vcc h then current source is on, output is pulsing typical values are: vcc h = 12 v, vcc l = 10 v to better understand the operational principle, figure 3 's sketch offers the necessary light: figure 3. the charge/discharge cycle over a 10 f v cc capacitor 10.0 m 30.0 m 50.0 m 70.0 m 90.0 m v cc current source off on output pulses v ripple = 2 v uvlo h = 12 v uvlo l = 10 v the dss behavior actually depends on the internal ic consumption and the mosfet's gate charge qg. if we select a mosfet like the mtp2n60e, qg max equals 22 nc. with a maximum switching frequency of 70 khz for the p60 version, the average power necessary to drive the mosfet (excluding the driver efficiency and neglecting various voltage drops) is: f sw ? qg ? v cc with f sw = maximum switching frequency qg = mosfet's gate charge v cc = v gs level applied to the gate to obtain the final ic current, simply divide this result by v cc : i driver = f sw ? qg = 1.54 ma. the total standby power consumption at noload will therefore heavily rely on the internal ic consumption plus the above driving current (altered by the driver's efficiency). suppose that the ic is supplied from a 350 vdc line. the current flowing through pin 8 is a direct image of the ncp1200a consumption (neglecting the switching losses of the hv current source). if icc2 equals 2.3 ma @ t j = 25 c, then the power dissipated (lost) by the ic is simply: 350 x 2.3 m = 805 mw. for design and reliability reasons, it would be interesting to reduce this source of wasted power which increases the die temperature. this can be achieved by using different methods: 1. use a mosfet with lower gate charge qg 2. connect pin through a diode (1n4007 typically) to one of the mains input. the average value on pin 8 becomes v mains(peak) 2 . our power contribution example drops to: 223 x 2.3 m = 512 mw. if a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. the resistor value should account for lowline startups. 3. permanently force the v cc level above vcc h with an auxiliary winding. it will automatically disconnect the internal startup source and the ic will be fully selfsupplied from this winding. again, the total power drawn from the mains will significantly decrease. make sure the auxiliary voltage never exceeds the 16 v limit.
ncp1200a http://onsemi.com 6 figure 4. 8 7 6 5 1 2 3 4 mains cbulk hv a simple diode naturally reduces the average voltage on pin 8 skipping cycle mode the ncp1200a automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level, the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the socalled skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches ( figure 6 ). suppose we have the following component values: lp, primary inductance = 1 mh f sw , switching frequency = 61 khz ip skip = 200 ma (or 333 mv/r sense ) the theoretical power transfer is therefore: 1 2 lp ip 2 f sw 1.2 w if this ic enters skip cycle mode with a bunch length of 20 ms over a recurrent period of 100 ms, then the total power transfer is: 1.2 . 0.2 = 240 mw. to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight: figure 5. skip cycle operation i p(min) = 333 mv/r sense normal current mode operation fb 1 v 4.2 v, fb pin open 3.2 v, upper dynamic range when fb is above the skip cycle threshold (1 v by default), the peak current cannot exceed 1 v/r sense . when the ic enters the skip cycle mode, the peak current cannot go below vpin1 / 3.3. the user still has the flexibility to alter this 1 v by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. grounding pin 1 permanently invalidates the skip cycle operation.
ncp1200a http://onsemi.com 7 power p1 power p2 power p3 figure 6. output pulses at various power levels (x = 5.0 s/div) p1 p2 p3 figure 7. 315.40 882.70 1.450 m 2.017 m 2.585 m 300 m 200 m 100 m 0 max peak current skip cycle current limit the skip cycle takes place at low peak currents which guaranties noisefree operation we recommend a pin1 operation between 400 mv and 1.3 v that will fix the skip peak current level between 120 mv / r sense and 390 mv / r sense . nonlatching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the adj pin 1 level, the output pulses are disabled as long as fb is pulled below pin 1. as soon as fb is relaxed, the ic resumes its operation. figure 8 depicts the application example:
ncp1200a http://onsemi.com 8 figure 8. on/off q1 8 7 6 5 1 2 3 4 another way of shutting down the ic without a definitive latchoff state power dissipation the ncp1200a is directly supplied from the dc rail through the internal dss circuitry. the average current flowing through the dss is therefore the direct image of the ncp1200a current consumption. the total power dissipation can be evaluated using: (v hvdc 11 v) ? icc2. if we operate the device on a 250 vac rail, the maximum rectified voltage can go up to 350 vdc. however, as the characterization curves show, the current consumption drops at high junction temperature, which quickly occurs thanks to the dss operation. at t j = 50 c, icc2 = 1.7 ma for the 61 khz version over a 1 nf capacitive load. as a result, the ncp1200a will dissipate 350 . 1.7 ma@t j = 50 c = 595 mw. the so8 package offers a junctiontoambient thermal resistance r q ja of 178 c/w. adding some copper area around the pcb footprint will help decreasing this number: 12 mm x 12 mm to drop r q ja down to 100 c/w with 35 m copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m copper thickness (2 oz.). with this later number, we can compute the maximum power dissipation the package accepts at an ambient of 50 c: pmax t jmax t amax r ja 750 mw which is okay with our previous budget. for the dip8 package, adding a minpad area of 80 mm of 35 m copper (1 oz.), r q ja drops from 100 c/w to about 75 c/w. in the above calculations, icc2 is based on a 1 nf output capacitor. as seen before, icc2 will depend on your mosfet's qg: icc2 icc1 + f sw x qg. final calculation shall thus accounts for the total gatecharge qg your mosfet will exhibit. the same methodology can be applied for the 100 khz version but care must be taken to keep t j below the 125 c limit with the d100 (soic) version and activated dss in highline conditions. if the power estimation is beyond the limit, other solutions are possible a) add a series diode with pin 8 (as suggested in the above lines) and connect it to the half rectified wave. as a result, it will drop the average input voltage and lower the dissipation to: 350 2 1.7 m 380 mw b) put an auxiliary winding to disable the dss and decrease the power consumption to v cc x icc2. the auxiliary level should be thus that the rectified auxiliary voltage permanently stays above 10 v (to not reactivate the dss) and is safely kept below the 16 v maximum rating. overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true shortcircuit protection. a shortcircuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the fb pin level is pulled up to 4.2 v, as internally imposed by the ic. the peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects. please note that this can also happen in case of feedback loss, e.g. a broken optocoupler. to account for this situation, ncp1200a hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low dutycycle. the system autorecovers when the fault condition disappears. during the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. this period of time depends on normal output load conditions and the maximum peak current allowed by the system. the timeout used by this ic works with the v cc decoupling capacitor: as soon as the v cc decreases from the uvlo h level (typically 12 v) the device internally watches for an overload current situation. if this condition is still present when the uvlo l level is reached, the controller stops the driving pulses, prevents the selfsupply current source to restart and puts all the circuitry in standby, consuming as little as 350 m a typical (icc3 parameter). as a result, the v cc level slowly discharges toward 0.
ncp1200a http://onsemi.com 9 driver pulses driver pulses time time time drv v cc 12 v 10 v 6 v regulation occurs here internal fault flag fault is relaxed fault occurs here latchoff phase startup phase figure 9. if the fault is relaxed during the v cc natural fall down sequence, the ic automatically resumes. if the fault still persists when v cc reached uvlo l , then the controller cuts everything off until recovery. when this level crosses 6 v typical, the controller enters a new startup phase by turning the current source on: v cc rises toward 12 v and again delivers output pulses at the uvlo h crossing point. if the fault condition has been removed before uvlo l approaches, then the ic continues its normal operation. otherwise, a new fault cycle takes place. figure 9 shows the evolution of the signals in presence of a fault. calculating the v cc capacitor as the above section describes, the fall down sequence depends upon the v cc level: how long does it take for the v cc line to go from 12 v to 10 v? the required time depends on the startup sequence of your system, i.e. when you first apply the power to the ic. the corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12 v to 10 v, otherwise the supply will not properly start. the test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. let's suppose that this time corresponds to 6 ms. therefore a v cc fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. if the corresponding ic consumption, including the mosfet drive, establishes at 1.8 ma for instance, we can calculate the required capacitor using the following formula: t v c i , with d v = 2 v. then for a wanted d t of 10 ms, c equals 9 m f or 10 m f for a standard value. when an overload condition occurs, the ic blocks its internal circuitry and its consumption drops to 350 m a typical. this happens at v cc = 10 v and it remains stuck until v cc reaches 6 v: we are in latchoff phase. again, using the calculated 10 m f and 350 m a current consumption, this latchoff phase lasts: 109 ms.
ncp1200a http://onsemi.com 10 package dimensions pdip8 n suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040
ncp1200a http://onsemi.com 11 package dimensions so8 d1, d2 suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
ncp1200a http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp1200a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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